1. Technical Field
The present invention relates to a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. More particularly, the present invention relates to a wafer level chip scale package having a sacrificial layer capable of inducing a crack which otherwise may be generated in a solder joint, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package.
2. Description of the Related Art
In order to meet consumer demand, electronic products are becoming smaller, lighter, and faster while their capacities are increasing. As demand for miniaturization of the electronics products increases, a semiconductor chip package is becoming smaller and lighter. The small semiconductor chip package may be, for example, a wafer level chip scale package or a wafer level package. The wafer level chip scale package is a package in which a semiconductor chip is not separated from a wafer prior to packaging during a manufacturing process.
FIG. 1 is a sectional view of a wafer level chip scale package 100 according to a conventional technology. Referring to FIG. 1, the wafer level chip scale package 100 includes a wafer having a semiconductor chip 105, an aluminum pad 110, a passivation layer 115, a first insulating layer 120, a redistribution line or rerouting line metal layer 125, a second insulating layer 130, and a solder ball 135 that is an external connection terminal.
In the manufacturing process of the wafer level chip scale package 100, the first insulating layer 120, which may be an interlayer dielectric material, is applied over a wafer. The aluminum pad 110, which is a bonding pad, is exposed using a photolithography process, including a film exposure process and a development process. The redistribution line metal layer 125 is formed on the first insulating layer 120 and the aluminum pad 110 through a sputtering process. Photoresist is coated on the redistribution line metal layer 125. A portion of the redistribution line metal layer 125, excluding a redistribution line or retribution pattern and a redistribution pad, is removed through the photolithography process. The redistribution pad is a part of the redistribution line where the solder ball 135 is attached and is referred to as a ball land. After the second insulating layer 130, that is the interlayer dielectric material, is applied, the redistribution pad is exposed using a photolithography process. Then, the solder ball 135 is attached on the redistribution pad through a solder ball attachment process, thereby completing the wafer level chip scale package 100.
The wafer level chip scale package 100 is mounted on a module substrate or a module PCB (printed circuit board) to form a semiconductor chip module. When a temperature cycle test is performed on the semiconductor chip module, a crack can be generated in the solder joint that is a connecting portion between the solder ball 135 and the redistribution pad. FIG. 2 is an SEM (scanning electron microscope) image showing the crack generated in the solder joint of the wafer level chip scale package 100.
The crack can be generated due to thermal stress and can be attributable to a difference in the coefficient of thermal expansion (CTE) between the semiconductor chip 105 and the module substrate. As the reliability of the solder joint is deteriorated by the crack, the reliability of the semiconductor chip module can be decreased. Thus, a wafer level chip scale package which can minimize defects of a semiconductor chip module due to the solder joint crack is needed.